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WInSiC4AP core objective is to contribute in developing reliable technology bricks for efficient and cost-effective applications addressing social challenges and market segments where Europe is a recognized global leader as well as automotive, avionics, railway and defence.

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WInSiC4AP approach is to rely on the strength of vertical integration allowing optimization, technologies fitting application requirements, developing the full ecosystem and approach relevant issues as reliability in the full scope.
That enhances the competitiveness of EU- Industries as well as TIER1 and TIER2 down to the value chain in a market context where other countries today, such as the USA or Japan, are advancing and new players accessing SiC enter in the market. New topologies and architecture will be developed for targeted application simulating operational environment, at laboratory level, driving the needed and still missed technologies, components and demonstrators to fill the gap between current state of the art and the very high demanding specifications.

WInSiC4AP framework has been built so that companies working in different domains (i.e. automotive car maker and TIER1-2 and avionics, railway and defence TIER1-TIER2) and in the vertical value chain (semiconductor suppliers, companies manufacturing inductors and capacitors) as well as academic entities and laboratories will collaborate to codesign solutions, solve problems and exchange know-how, such that unforeseen results may also emerge. WInSiC4AP will be supported with synergy between ECSEL JU and ESI funding enabling complementary activities with relevant economic and social impact envisage in a less development region of Union.

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This project has received funding from the Electronic Component Systems for European Leadership Joint Undertaking (ECSEL JU) under grant agreement No.737483. This Joint Undertaking receives support from the European Union’s Horizon 2020 research and innovation programme and Czech Republic, France, Germany, Italy.

This project also receives ESI funds from MIUR 2014-2020 FESR program.